Examiner Brian J Assessor has allowed 28 of 36 decided applications in Computer Architecture, Software, and Information Security.
Examiner Brian J Assessor has an overall allowance rate of 78% across dozens of decided (allowed plus abandoned) applications, spanning 2 art units in Technology Center 2100 (Computer Architecture, Software, and Information Security). These are pooled figures from the public USPTO record, not predictions about any specific application.
This page pools Examiner Brian J Assessor's record across 2 art units into one overall allowance rate — total allowed divided by total decided (allowed plus abandoned) applications, with pending excluded. Aggregate figures describe the past public record and are not predictions about any specific application. This is general information about the data, not legal advice.
These are aggregate statistics from this examiner's past public record — not predictions about any specific application. The per-art-unit figures below show how the record varies across art units. Our approach to patent prosecution →
Each section benchmarks this examiner against that art unit's average. Figures are this examiner's own public record within the art unit; the overall rate above pools them.
Primarily examines error detection, correction, and monitoring.
Primarily examines neural-network / biological-model computing, and machine learning.
Grounds can co-occur, so the four don't sum to 100%. The art-unit figure is the unweighted mean across examiners in the art unit; §102 and §112 carry no art-unit benchmark.
Based on 2 applications — too small a sample to characterize the rejection mix reliably; shown for completeness.
Lynch LLP represents applicants in patent prosecution before the USPTO. These are general resources about the firm's services — not advice about this examiner or any specific application.
Methodology. This page pools every art unit in which Examiner Brian J Assessor has a public record within Technology Center 2100. Statistics are computed from publicly available USPTO records, refreshed on a recurring schedule. This page's data was last updated July 14, 2026. The overall allowance rate is total allowed divided by total decided applications (allowed plus abandoned) across all art units — not an average of the per-art-unit rates; pending applications are excluded. Figures are rounded for display. Pooled sample: 36 applications.
Rejection rates. Each §-rate is the share of this examiner's applications that drew at least one office-action rejection in which that statutory ground appears; applications with no rejection on record are excluded, and because grounds can co-occur the four do not sum to 100%. The art-unit figure beside each is the unweighted mean of the per-examiner rates across the art unit, published for §101 and §103 only. Beside the overall allowance rate we show a benchmark: for a single-art-unit examiner it is exactly that art unit's average, labeled “art-unit average”; for an examiner spanning several art units it is the “weighted peer average” — the per-art-unit averages, weighted by this examiner's application count in each — labeled distinctly because it is a blended figure, not any single art unit's average. Both are built from the same per-art-unit averages the panels show.
Lynch LLP is not affiliated with, endorsed by, or sponsored by the United States Patent and Trademark Office. Examiner statistics are derived from publicly available USPTO data.
These statistics describe past examiner behavior and do not predict the outcome of any particular application. Past results do not guarantee future outcomes. Where this page compares an examiner's allowance rate to an art-unit average, that comparison is a factual description of the public record, not a characterization of any individual examiner's conduct or competence.
This page is for general informational purposes and is not legal advice. No attorney-client relationship is formed by viewing it. Full disclaimers →
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