This examiner has a small public record (17applications), so we don't publish a record summary — small samples over-state patterns. The per-art-unit figures below are shown for completeness.
Each section benchmarks this examiner against that art unit's average. Figures are this examiner's own public record within the art unit; the overall rate above pools them.
Primarily examines input/output (I/O) data transfer, and memory access and allocation.
Based on 10 applications — too small a sample to characterize the rejection mix reliably; shown for completeness.
Primarily examines computer-aided design (CAD).
Methodology. This page pools every art unit in which Examiner Mano Padmanabhan has a public record within Technology Center 2100. Statistics are computed from publicly available USPTO records, refreshed on a recurring schedule. This page's data was last updated June 25, 2026. The overall allowance rate is total allowed divided by total decided applications (allowed plus abandoned) across all art units — not an average of the per-art-unit rates; pending applications are excluded. Figures are rounded for display. Pooled sample: 17 applications.
Lynch LLP is not affiliated with, endorsed by, or sponsored by the United States Patent and Trademark Office. Examiner statistics are derived from publicly available USPTO data.
These statistics describe past examiner behavior and do not predict the outcome of any particular application. Past results do not guarantee future outcomes. Where this page compares an examiner's allowance rate to an art-unit average, that comparison is a factual description of the public record, not a characterization of any individual examiner's conduct or competence.
This page is for general informational purposes and is not legal advice. No attorney-client relationship is formed by viewing it. Full disclaimers →
ATTORNEY ADVERTISING — Sean Lynch, Partner, Lynch LLP