Examiner Sathyanaraya R Pannala has allowed 209 of 295 decided applications (71%) in Computer Architecture, Software, and Information Security.
Examiner Sathyanaraya R Pannala maintains a public record across 3 art units within Technology Center 2100 (Computer Architecture, Software, and Information Security). Over 295 disposed applications, the examiner allowed 209 and abandoned 86, for an overall allowance rate of 71%. Across the examiner's art units, allowance rates range from 70% to 73%. This pooled figure reflects decisions made across multiple art units and represents the examiner's historical record in this technology center.
A pooled record aggregates data from multiple art units, presenting an overall allowance rate and range. The 71% figure describes past outcomes across 295 decided applications and is not a prediction of any specific application. The range (70% to 73%) shows variation among individual art units, which are examined separately elsewhere. Pooled statistics describe historical patterns, not future results for any particular case.
These are aggregate statistics from this examiner's past public record — not predictions about any specific application. The per-art-unit figures below show how the record varies across art units. Our approach to patent prosecution →
Each section benchmarks this examiner against that art unit's average. Figures are this examiner's own public record within the art unit; the overall rate above pools them.
Primarily examines information retrieval and database structures.
Allowance rate for applications with an examiner interview versus without one.
A correlation, not proof that interviews cause allowances. Based on 133 decided applications with an interview and 131 without.
Primarily examines information retrieval and database structures.
Methodology. This page pools every art unit in which Examiner Sathyanaraya R Pannala has a public record within Technology Center 2100. Statistics are computed from publicly available USPTO records, refreshed on a recurring schedule. This page's data was last updated June 25, 2026. The overall allowance rate is total allowed divided by total decided applications (allowed plus abandoned) across all art units — not an average of the per-art-unit rates; pending applications are excluded. Figures are rounded for display. Pooled sample: 295 applications.
Lynch LLP is not affiliated with, endorsed by, or sponsored by the United States Patent and Trademark Office. Examiner statistics are derived from publicly available USPTO data.
These statistics describe past examiner behavior and do not predict the outcome of any particular application. Past results do not guarantee future outcomes. Where this page compares an examiner's allowance rate to an art-unit average, that comparison is a factual description of the public record, not a characterization of any individual examiner's conduct or competence.
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